A read-only-memory, hereinafter referred to as a ROM, can be made by forming a matrix of insulated gate field effect transistors, hereinafter referred to as IGFETs. The IGFETs are arranged on a common substrate in a pattern such that the gates of individual transistors are aligned in a number of parallel input columns, and the drains of individual devices in each column are aligned in a plurality of parallel rows. Accordingly, the drains of all IGFETs can be individually contacted by an overlying metallization pattern of parallel metal strips, which in plan view are orthoganol to the parallel input gate columns. All gates in a column have a common input, and the overlying metal strips form a common output for the drains in each row. Memory devices such as these are referred to in U.S. Pat. No. 3,541,543 Crawford et al., U.S. Pat. No. 3,914,855 Cheney et al. and U.S. Pat. No. 4,129,936 Takei.
IGFET ROMs can be programmed by not making IGFETs at selected locations in the matrix or by making the IGFETs at those locations inoperative. In the latter programming technique, all devices in the matrix are made to have operable sources and gates. However, the overlying metal strips electrically contact the drains of only those IGFETs selected to provide the desired ROM output response. On the other hand, it is recognized that ancillary factors dictate that the ROM must be made considerably larger, if one is to program it at the metallization step.
Consequently, it is also recognized as desirable to program the ROM by simply not making an IGFET at matrix locations where one is not desired. In such instance, the metallization mask is always the same, regardless of the program, and the resultant ROM can thus be smaller, more reliable, less expensive, etc. One can avoid not making an IGFET at desired matrix locations in a variety of ways. In one way, a field oxide is first grown on a silicon wafer. Windows are opened in the field oxide at every matrix location where an IGFET is desired. If one does not want to form an IGFET at any given matrix location, no field oxide window is opened at that location.
On the other hand, programming the ROM so early in its process of manufacture presents other problems, such as what to do with all the ROM wafers and chips already downstream in the manufacturing process when a programming change is made. One must either discard in-process ROMs, or wait until the newly programmed ROMs show up at the end of the manufacturing process flow. To avoid such problems, it has been proposed to program the ROM as late in its process of manufacture as possible but prior to metallization. This reduces losses due to in-process ROMs and/or reduces the delay before the newly programmed ROMs can be completed. This reprogramming delay is often referred to as turn-around time. Turn-around time can be reduced by reprogramming as far downstream in the process as possible. However, to avoid increasing circuit cost, the form of the reprogramming should not require any appreciable increase in ROM size.
U.S. Pat. No. 4,129,936 Takei describes making a matrix in which IGFETS at all locations would be operable. However, ion implantation, using a photo-resist layer as a mask, is used to turn off selected IGFETs by increasing gate threshold voltage. However, it should be recognized that this form of reprogramming is not immediately prior to metallization. U.S. Pat. No. 3,914,855 Cheney et al. describe using ion implantation to increase selected gate threshold voltage after metallization. Windows are provided in the metallization layer over selected IGFET gates so that those gates can be turned off by the ion beam. However, this requires a contact mask change. In addition the nature of the change is such that metallization runners must be made wide enough to go around the gates where the windows are located, and surface areas must be left on the wafer metallization layer where selected IGFETs are to be made inoperative. However, this requires contact mask change. In addition the nature of the change is such that metallization runners must be made wide enough to go around the gates where the windows are located, and surface area must be left on the wafer between devices to allow the runners to go around the gates. Another approach is disclosed in an article entitled "ROM Program Process May Beat EPROMs in Turnaround Time", appearing on pages 39 and 40 of the May 25, 1978 issue of Electronics. I understand that in this latter technique the implant is done after metallization, which inherently expands ROM size and special packaging.
I have found an ion implantation technique that can be used to program the ROM immediately before metallization. Also, the metallization pattern need not be widened, and no protective coating need be formed on the gate electrode after reprogramming and before metallization. Still further, I have found how to combine this reprogramming technique with a technique that insures good contacts to source and drain regions, even if contact masks are slightly misaligned or undesirable lateral contact window etching occurs for other reasons.